Photonics and Electronics Research Lab

High-Speed CMOS ADC Design

Silicon Germanium (SiGE) and Gallium Arsenide (GaAs) technologies have been long recognized as dominant technologies for RF and high-speed ADC design. On the other hand, digital signal processing (DSP) components of electronic systems are usually implemented in Complementary Metal Oxide Semiconductor (CMOS) technology. The increasing need for system integration has caused CMOS technology, whose speed has continuously advanced following Moore’s law, to emerge as a promising alternative in high-speed ADC design due to its low cost, ever-increasing speed, and integration capability with DSP. As a result, realization of a CMOS medium-resolution high-speed ADC with sampling rate exceeding 50 Gs/s has been the motivation for many research projects in recent years. In this project, we are developing 100-GS/s ADC in 65-nm CMOS process technology. There are many challenges due to requirements of low-jitter clock generation and distribution, very high sampling rates, wide bandwidth, and signal distribution as well as interconnect issue.

Other challenges include decreasing supply voltages and increasing device mismatch. All these challenges will be addressed in our design.

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Prof Christina Lim

Director, Photonics and Electronics